Software Design Flow for an Arm*-based Intel® SoC FPGA (OSOC2000)

27 Minutes Online Course

Course Description

This course is intended for low level software and firmware engineers and examines the software design flow required to implement software for an Intel® SoC FPGA with the ARM*-based HPS as an FPGA Component IP. This course discusses the tools and methodology necessary to design and verify your system software. You will gain an understanding of exactly what’s required to implement your software with Intel SoC FPGAs.

*HPS = hard processor system

At Course Completion

You will be able to:

  • Explain the software development tools provided in the Intel SoC FPGA Embedded Development Suite (SoC EDS)
  • Explain the boot flow of the HPS as an FPGA Component IP
  • Create the second stage bootloader software from hardware software handoff files
  • Use the Intel SoC EDS and hardware libraries to create a bare-metal or OS specific application
  • Select an operating system to run on the Arm processor
  • Perform FPGA-adaptive debug

Skills Required

  • Basic software development knowledge

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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