Hardware Design Flow for an Arm*-based Intel® SoC FPGA (OSOC1000)

Course Description

This course is intended for hardware and firmware engineers and examines the hardware design flow required to implement an Intel® SoC FPGA with the ARM*-based HPS as an FPGA Component IP. This course discusses the tools and methodology necessary to design and verify your system. You will gain an understanding of exactly what’s required to implement a good system with Intel SoC FPGAs.

*HPS = hard processor system

At Course Completion

You will be able to:

• Create an Intel SoC FPGA system using the Intel Quartus® Prime software and Platform Designer system integration tool
• Understand the necessary steps to create a custom component that interacts with the HPS as an FPGA Component IP
• Run a functional simulation of your custom component or system using provided bus functional models
• Debug using the System Console tool
• Understand features included in Intel FPGA development tools to perform FPGA-adaptive software debug

Skills Required

• FPGA knowledge is not required, but a plus

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Software Design Flow for an Arm*-based Intel® SoC FPGA

Related Courses

Below are the related courses you may be interested in:

• SoC Hardware Overview: Flash Controllers and Interface Protocols
• SoC Hardware Overview: Interconnect and Memory
• SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals
• SoC Hardware Overview: the Microprocessor Unit

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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