Hardware Design Flow for an ARM-based SoC (OSOC1000)

40 Minutes Online Course

Course Description

This course is intended for hardware and firmware engineers and examines the hardware design flow required to implement an Altera® SoC with the ARM®-based hard processing system (HPS). This course discusses the tools and methodology necessary to design and verify your SoC system. You will gain an understanding of exactly what’s required to implement a good system with Altera’s SoC devices.

At Course Completion

You will be able to:

  • Create an SoC system using the Quartus® software and Qsys system integration tool
  • Understand the necessary steps to create a custom component that interacts with the HPS
  • Run a functional simulation of your custom component or system using provided BFMs
  • Debug an SoC with the System Console tool
  • Understand features included in Altera tools to perform FPGA-adaptive software debug

Skills Required

  • FPGA knowledge is not required, but a plus

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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