Transceiver Basics for 20 nm and 28 nm Devices (OSIIGX1115)

Course Description

High-speed transceiver-based FPGAs are mainstream devices in the programmable logic space today. This online course provides an overview of the transceivers found in transceiver-based Altera® FPGAs in the Quartus® II software version 13.1. By the end of this training, you will be able to define the blocks found in the both the transmitter and receiver data paths along with their purposes. You will also be able to specify which blocks make up the digital physical coding sub-layer (PCS) and the analog physical media attachment (PMA).

At Course Completion

You will be able to:

• Describe the blocks found in the transmitter and receiver paths of FPGA high-speed serial transceivers
• Define which blocks make up the physical coding sub-layer and which make up the physical media attachment

Skills Required

• Background in digital logic
• General understanding of FPGA architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Custom Protocol Design in Altera 28-nm Devices (Legacy Course)
• Getting Started with Altera's 40 nm PCI Express Solutions
• High-Speed Serial Protocol Design with Altera Transceiver Devices (Legacy Course)
• Introduction to the Triple-Speed Ethernet MegaCore Function

Related Courses

Below are the related courses you may be interested in:

• Migrating to the Quartus Prime Pro Edition Software

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• I/O Interfaces

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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