SEU Mitigation in Intel® FPGA Devices: Fault Injection (OSEUFAULT)

14 Minutes Online Course

Course Description

As cloud-based services continue to grow, protection of that cloud data is even more important, such that single event upsets (SEU) are not just the concern of avionics and safety critical systems. With that in mind, this online training, SEU Mitigation in Intel® FPGA Devices: Fault Injection, discusses how to set up your Intel FPGA design to perform hardware simulations of SEUs.

In this training, you get a brief review of the SEU features that exist for certain Intel FPGA devices. You then learn about fault injection and how it relates to Intel FPGA devices. You learn about the Fault Injection, Error Message Register, and Advanced SEU Detection IP cores. Finally, you learn about the Fault Injection Debugger software and how it works with the IP cores.

At Course Completion

You will be able to:

  • Enable Intel Arria 10 and Intel Cyclone 10 GX device features to reduce your Failures in Time (FIT) rate and to develop a SEU fault response solution
  • Employ the Error Message Register IP core to help mitigate SEUs
  • Employ the Advanced SEU Detection (ASD) IP core to improve your fault response by filtering SEU events
  • Employ the Fault Injection IP core to communicate with the Fault Injection Debugger software

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Intel® Quartus® Prime design software

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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