Building an Intel® Stratix® 10 FPGA Transceiver PHY Layer (OS10XCVRPHY)

39 Minutes Online Course

Course Description

In the Building an Intel® Stratix® 10 FPGA Transceiver PHY Layer course, you will learn how to define the three resources that make up an Intel Stratix 10 FPGA transceiver PHY layer solution, namely, the transceiver PHY, the transceiver PLL and the transceiver reset controller. To do this, you will learn how to configure the IP cores found in the Intel Quartus® Prime Pro development suite for all three Intel Stratix 10 FPGA tile types: L-Tiles, H-Tiles and E-Tiles. You will then learn how to properly connect the cores to construct a custom transceiver PHY solution.

At Course Completion

You will be able to:

  • Configure the Intel Stratix 10 FPGA PHY IP cores:
  • Intel Stratix 10 FPGA L-Tile/H-Tile Native PHY IP core
  • Intel Stratix 10 FPGA E-Tile Native PHY IP core
  • Intel Stratix 10 FPGA L-Tile/H-Tile Transceiver ATX PLL IP core
  • Intel Stratix 10 FPGA L-Tile/H-Tile fPLL IP core
  • Intel Stratix 10 FPGA L-Tile/H-Tile Transceiver CMU PLL IP core
  • Intel Stratix 10 FPGA Transceiver PHY Reset Controller IP core
  • Construct a transceiver custom PHY layer using the transceiver PHY IP cores

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with FPGA architecture
  • Familiarity with the Intel Quartus Prime Pro design software
  • Knowledge of Intel Stratix 10 FPGA transceiver architecture
  • Familiarity with high-speed interfaces and transmission protocols is helpful, but not required

Prerequisites

We recommend completing the following courses:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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