Intel® Quartus® Prime Software Hyper-Aware Design Flow (OS10TOOLS)

Course Description

In the Intel® Quartus® Prime Software Hyper-Aware Design Flow course, you will learn about two Intel Quartus Prime Pro software features, the Hyper-Retimer and Hyper-Aware CAD. Together these two features enable your designs to take full advantage of Hyper-Registers found in the Intel Hyper-Flex architecture of Intel Stratix® 10 FPGAs. You will then learn how you can further improve your clock speeds by analyzing retiming reports produced during compilation. Lastly, you will see how existing Quartus Prime Pro software tools have also been modified to support the understanding of Hyper-Register use.

At Course Completion

You will be able to:

• Use the Hyper-Retimer module to increase Intel Stratix 10 FPGA compilation results
• Describe how Hyper-Aware CAD settings to improve the effectiveness of your FPGA’s placement and routing

Skills Required

• Familiarity with FPGA/CPLD design flow
• Familiarity with the Quartus Prime Pro design software

Prerequisites

We recommend completing the following courses:

• Stratix® 10 HyperFlex™ Architecture Overview
• The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer
• The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
• The Quartus Prime Software: Foundation (Standard Edition) (Online Training)
• Timing Analyzer: Introduction to Timing Analysis
• Timing Closure with the Quartus II Software

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Advanced Optimization with Intel® Stratix® 10 FPGA Hyperflex™ Architecture
• Using Fast Forward Compile for the Intel® HyperFlex™ Architecture

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• Advanced Hardware

Class Schedule

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