Course DescriptionIn this training you will learn about the architecture of the Intel® Stratix® 10 SoC FPGA. You will learn about the Hard Processor System (HPS) and its contents. We begin by discussing the ARM* Cortex*-A53 MPCore*. The Cache Coherency Unit (CCU) and System MMU (SMMU) memory management blocks are explained next. The bridges between the HPS, FPGA, and SDRAM are also discussed. You will also get an overview of the embedded software ecosystem for the Intel Stratix 10 SoC including Linux, HWLIBs, and SoCEDS. Finally, the training will give an overview of the boot flow of the device, which will include an explanation of the role the Secure Device Manager (SDM) plays.
*Other names and brands may be claimed as the property of others.
At Course Completion
You will be able to:
- Understand the architecture of the Intel Stratix 10 SoC FPGA HPS
- Understand the CCU and SMMU memory management blocks
- Understand the software ecosystem for the Intel Stratix 10 SoC
- Explain the boot flow for the Intel Stratix 10 SoC
- Basic knowledge of computer architecture
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
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