Hyper-Optimization Techniques 3: Shannon’s Decomposition (OS10SHAN)

Course Description

Are you targeting a Stratix® 10 device and wanting to learn how your design can reach the maximum core performance?

The is the 3rd of 3 online courses that teaches advanced optimization techniques for the Stratix 10 HyperFlex™ Architecture.

In this course, you will learn how to use Shannon’s Decomposition to shrink critical chain loops to achieve breakthrough levels of operating clock frequency (fmax) in your design thus unleashing the full potential of the Stratix 10 HyperFlex architecture.

Note: While the focus of this course is the Stratix 10 device family, many of the techniques you will learn can be used to improve performance in other device architectures.

At Course Completion

You will be able to:

• Apply Shannon’s Decomposition to shrink critical chain loops

Skills Required

• Familiarity with FPGA/CPLD design flow
• Familiarity with the Quartus® II design software
• Familiarity with Verilog or VHDL synthesizable design structures

Prerequisites

We recommend completing the following courses:

• Hyper-Optimization Techniques 2: Pre-Computation
• Intel® Stratix® 10 FPGA Optimization: Loop Analysis and Solutions
• Introduction to Hyper-Optimization
• The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer
• The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
• The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
• Timing Analyzer: Introduction to Timing Analysis
• Timing Closure with Intel® Quartus® Prime Pro Software

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Advanced Optimization with Intel® Hyperflex™ Architecture

Related Courses

Below are the related courses you may be interested in:

• SoC Hardware Overview: the Microprocessor Unit
• Software Design Flow for an ARM-based SoC

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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