Are you targeting a Stratix® 10 device and wanting to learn how your design can reach the maximum core performance?
The is the 2nd of 3 online courses that teaches advanced optimization techniques for the Stratix 10 HyperFlex™ Architecture.
In this course, you will learn to use pre-computation techniques to shrink critical chain loops to achieve breakthrough levels of operating clock frequency (fmax) in your design thus unleashing the full potential of the Stratix 10 HyperFlex architecture.
Note: While the focus of this course is the Stratix 10 device family, many of the techniques you will learn can be used to improve performance in other device architectures.
At Course Completion
You will be able to:
- Learn the Hyper-Optimization restructuring technique of moving loops from feedback to feedforward
- Reduce loop size to lessen the impact on Hyper-Retiming
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus® II design software
- Familiarity with Verilog or VHDL synthesizable design structures
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: