Are you targeting a Stratix® 10 HyperFlex™ device and wanting to learn how your design can reach the maximum core performance?
This is the 1st of several online courses that teach advanced optimization techniques for the Stratix 10 HyperFlex Architecture. In this course, you will learn about different types of loops that appear in FPGA designs. You will then learn about some potential solutions for removing loops or minimizing their impact to your design’s maximum operating clock frequency (fmax).
At Course Completion
You will be able to:
- Understand common loop structures found in FPGA designs
- Employ simple techniques to reduce the impact of loops on performance
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus® design software
- Familiarity with Verilog or VHDL synthesizable design structures
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
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