Introduction to Hyper-Retiming (OS10IHYPRET)
Course Description
In the Introduction to Hyper-Retiming course, you will learn how to employ Hyper-Retiming, the first of three optimization steps to improving your design’s performance with the Intel® Hyperflex™ architecture, with each step allowing you to move you up the performance curve. This course will show you how Hyper-Retiming works and the advantages Hyper-Retiming has over traditional forms of retiming used in conventional FPGA architectures today.
At Course Completion
You will be able to:
- Define how Hyper-Retiming differs from conventional retiming
- Describe how Hyper-Retiming works in Intel Agilex and Intel Stratix 10 devices
Skills Required
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus® Prime software
- Familiarity with Verilog or VHDL synthesizable design structures
Prerequisites
We recommend completing the following courses:
- The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer
- The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
- The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
- Timing Analyzer: Introduction to Timing Analysis
- Timing Closure with Intel® Quartus® Prime Pro Software
- Using Fast Forward Compile for the Intel® HyperFlex™ Architecture
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
Class Schedule
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Location | Dates | Price | Registration |
---|---|---|---|
On-line | Anytime | Free | Register Now |