Introduction to Hyper-Pipelining (OS10HYPPIPE)

Course Description

Hyper-Pipelining is the second of three steps to improving your design’s performance when targeting the Intel® Hyperflex™ architecture found in Intel Agilex™ and Intel Stratix® 10 FPGAs, with each step allowing you to move you up the performance curve. In this training, you will learn the meaning of Hyper-Pipelining, how it differs from conventional pipelining and how to implement Hyper-Pipelining in your design with the help of the Intel Quartus® Prime Pro software’s Fast Forward analysis tool.

At Course Completion

You will be able to:

• Improve your Intel Hyperflex architecture design performance by implementing zero-latency Hyper-Pipelining

Skills Required

• Familiarity with FPGA/CPLD design flow
• Familiarity with the Intel Quartus Prime Pro design software
• Familiarity with Verilog or VHDL synthesizable design structures
• Familiarity with the Intel Hyperflex architecture

Prerequisites

We recommend completing the following courses:

• Eliminating Barriers to Hyper-Retiming
• Intel® Quartus® Prime Software Hyper-Aware Design Flow
• Introduction to Hyper-Retiming
• Stratix® 10 HyperFlex™ Architecture Overview
• The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer
• The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
• The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
• Timing Analyzer: Introduction to Timing Analysis
• Timing Closure with Intel® Quartus® Prime Pro Software
• Using Fast Forward Compile for the Intel® HyperFlex™ Architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Advanced Optimization with Intel® Hyperflex™ Architecture
• Hyper-Optimization Techniques 2: Pre-Computation
• Hyper-Optimization Techniques 3: Shannon’s Decomposition
• Intel® Stratix® 10 FPGA Optimization: Loop Analysis and Solutions
• Introduction to Hyper-Optimization

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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