Introduction to Hyper-Pipelining (OS10HYPPIPE)

28 Minutes Online Course

Course Description

Hyper-Pipelining is the second of three steps to improving your design’s performance when targeting the Intel® Hyperflex™ architecture found in Intel Stratix® 10 FPGAs, with each step allowing you to move you up the performance curve. In this training, you will learn the meaning of Hyper-Pipelining, how it differs from conventional pipelining and how to implement Hyper-Pipelining in your design with the help of the Intel Quartus® Prime Pro software’s Fast Forward Compile analysis tool.

At Course Completion

You will be able to:

  • Improve your Intel Stratix 10 design performance by implementing zero-latency Hyper-Pipelining

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Intel Quartus Prime Pro design software
  • Familiarity with Verilog or VHDL synthesizable design structures
  • Familiarity with the Intel Stratix 10 FPGA or Intel Hyperflex architecture

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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