Introduction to Hyper-Optimization (OS10HYPOPT)
Course Description
Are you targeting an Intel® Stratix® 10 FPGA and wanting to learn how your design can reach the maximum core performance?
This course will give you an introduction to advanced optimization techniques for the HyperFlex™ architecture found in Stratix 10 FPGAs. In this course, you will learn about design practices that limit the effectiveness of Hyper-Retiming and Hyper-Pipelining and about Hyper-Optimization techniques that can be used to to overcome those bottlenecks thus unleashing the full potential of the HyperFlex architecture.
At Course Completion
You will be able to:
- Understand factors that may reduce the effectiveness of Hyper-Retiming and Hyper-Pipelining
- Locate and evaluate loop structures that reduce design performance
Skills Required
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus® Prime Pro design software
- Familiarity with Verilog or VHDL synthesizable design structures
Prerequisites
We recommend completing the following courses:
- Intel® Quartus® Prime Software Hyper-Aware Design Flow
- Introduction to Hyper-Pipelining
- Introduction to Hyper-Retiming
- Performance Optimization with Intel® Stratix® 10 FPGA Hyperflex™ Architecture
- Stratix® 10 HyperFlex™ Architecture Overview
- The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer
- The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
- The Quartus Prime Software: Foundation (Standard Edition) (Online Training)
- Timing Analyzer: Introduction to Timing Analysis
- Timing Closure with Intel® Quartus® Prime Pro Software
- Using Fast Forward Compile for the Intel® HyperFlex™ Architecture
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: