Are you targeting an Intel® Agilex™ or Intel Stratix® 10 FPGA and wanting to learn how your design can reach the maximum core performance?
This course will give you an introduction to advanced optimization techniques that can be useful when targeting Intel FPGAs equipped with the Intel HyperFlex™ architecture. In this course, you will learn about design practices that limit the effectiveness of Hyper-Retiming and Hyper-Pipelining and about Hyper-Optimization tools and techniques that can be used to to overcome those bottlenecks, unleashing the full potential of the Intel HyperFlex architecture.
At Course Completion
You will be able to:
- Understand factors that may reduce the effectiveness of Hyper-Retiming and Hyper-Pipelining
- Locate and evaluate loop structures that reduce design performance using the Fast Forward analysis feature of the Intel Quartus Prime Pro software
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus Prime Pro software
- Familiarity with Verilog or VHDL synthesizable design structures
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: