Introduction to Hyper-Optimization (OS10HYPOPT)

Course Description

Are you targeting an Intel® Agilex™ or Intel Stratix® 10 FPGA and wanting to learn how your design can reach the maximum core performance?

This course will give you an introduction to advanced optimization techniques that can be useful when targeting Intel FPGAs equipped with the Intel HyperFlex™ architecture. In this course, you will learn about design practices that limit the effectiveness of Hyper-Retiming and Hyper-Pipelining and about Hyper-Optimization tools and techniques that can be used to to overcome those bottlenecks, unleashing the full potential of the Intel HyperFlex architecture.

At Course Completion

You will be able to:

• Understand factors that may reduce the effectiveness of Hyper-Retiming and Hyper-Pipelining
• Locate and evaluate loop structures that reduce design performance using the Fast Forward analysis feature of the Intel Quartus Prime Pro software

Skills Required

• Familiarity with FPGA/CPLD design flow
• Familiarity with the Intel Quartus Prime Pro software
• Familiarity with Verilog or VHDL synthesizable design structures

Prerequisites

We recommend completing the following courses:

• Intel® Quartus® Prime Software Hyper-Aware Design Flow
• Introduction to Hyper-Pipelining
• Introduction to Hyper-Retiming
• Performance Optimization with Intel® Stratix® 10 FPGA Hyperflex™ Architecture
• Stratix® 10 HyperFlex™ Architecture Overview
• The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer
• The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
• The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
• Timing Analyzer: Introduction to Timing Analysis
• Timing Closure with Intel® Quartus® Prime Pro Software
• Using Fast Forward Compile for the Intel® HyperFlex™ Architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Advanced Optimization with Intel® Stratix® 10 FPGA Hyperflex™ Architecture
• Hyper-Optimization Techniques 2: Pre-Computation
• Hyper-Optimization Techniques 3: Shannon’s Decomposition
• Intel® Stratix® 10 FPGA Optimization: Loop Analysis and Solutions

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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