Course DescriptionThis online course will introduce the IP core used to customize the Hard IP for Ethernet block found in Intel® Agilex™ F-Series and Intel Stratix® 10 FPGA MX/TX/DX FPGA E-Tiles. The course begins with a description of the optional various configurations of the core that are supported. It then defines some of the features you can select when customizing the core for your target design. The course ends with showing you how to use the parameter editor found in the IP Catalog of the Intel® Quartus® Prime Pro to perform those customizations.
At Course Completion
You will be able to:
- Describe the features and functionality of the Hard IP for Ethernet found in Intel® Agilex™ F-Series and Intel Stratix® 10 FPGA MX/TX/DX FPGA E-Tiles
- Customize your own Hard IP for Ethernet using the IP Catalog of the Intel Quartus® Prime Pro software
- Understanding of the Ethernet protocols, particularly 10G, 25G and 100G Ethernet
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus Prime design software
- Familiarity with Intel® FPGA E-Tile architecture OR viewing the following course: "Intel® FPGA E-Tile Transceiver Basics"
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: