Eliminating Barriers to Hyper-Retiming (OS10EHYPRET)

33 Minutes Online Course

Course Description

In the Eliminating Barriers to Hyper-Retiming course, you will gain a deeper understanding of Hyper-Retiming in learning what prevents the Hyper-Retimer module in the Intel® Quartus® Prime Pro software compile flow from using Intel Stratix® 10 FPGA Hyper-Registers to increase your design performance. You will also learn various design modifications you can implement that will help you to circumvent these barriers to Hyper-Retiming. Finally, you will learn how to use the Fast Forward analysis tool to take the guesswork out of this process, guiding you to the target retiming restrictions that should be removed to increase your designs clock speed.

At Course Completion

You will be able to:

  • Describe the design structures that prevent Hyper-Retiming
  • Make RTL changes to eliminate Hyper-Retiming restrictions
  • Use Fast Forward analysis to determine which restrictions should be removed

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Intel Quartus Prime Pro design software
  • Familiarity with Verilog or VHDL synthesizable design structures
  • Familiarity with the Intel Hyperflex architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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