Hyper-Retiming in the Intel® Quartus® Prime Pro software is a key to your FPGA designs reaching the highest performance in Intel® FPGAs built using the Intel Hyperflex™ architecture.
In the Eliminating Barriers to Hyper-Retiming course, you learn the circuit situations that prevent the Hyper-Retimer module from using Intel Agilex™ and Intel Stratix® 10 FPGA Hyper-Registers to increase your design performance. You will also learn various design modifications and constraints you can implement that will help you to circumvent these barriers to Hyper-Retiming. Finally, you will see how to use the Fast Forward analysis tool to take the guesswork out of this process, guiding you to the target retiming restrictions that could be removed to increase your designs clock speed.
At Course Completion
You will be able to:
- Describe the design structures that prevent Hyper-Retiming
- Make RTL changes to eliminate Hyper-Retiming restrictions
- Use Fast Forward analysis to determine which restrictions should be removed
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus Prime Pro design software
- Familiarity with Verilog or VHDL synthesizable design structures
- Familiarity with the Intel Hyperflex architecture
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: