Intel® Hyperflex™ FPGA Architecture Design: Analyzing Critical Chains (OS10CRCHNS)

Course Description

In the Intel® Hyperflex™ FPGA Architecture Design: Analyzing Critical Chains course, you will learn what is meant by the term “critical chain”, the report produced by the Intel Quartus® Prime software for designs targeting Intel Stratix® 10 FPGAs and you will discover how it relates to your design performance. By the end of the training, you will be able to use the Intel Quartus Prime tools to determine if your critical chain needs to be addressed and to read critical chain reports so as to correlate them to your Intel Stratix 10 FPGA design. You will also be able to apply some solutions to your critical chain to achieve higher clock speeds.

At Course Completion

You will be able to:

• Understand critical chains and how they relate to design performance
• Analyze critical chain reports to determine the design structure that generated them
• Locate resources necessary to solve critical chains

Skills Required

• Familiarity with FPGA/CPLD design flow
• Familiarity with the Intel Quartus Prime Pro development software including Hyper-Retiming and Fast Forward analysis
• Understanding of the Stratix 10 HyperFlex architecture

Prerequisites

We recommend completing the following courses:

• Eliminating Barriers to Hyper-Retiming
• Intel® Quartus® Prime Software Hyper-Aware Design Flow
• Introduction to Hyper-Retiming
• Stratix® 10 HyperFlex™ Architecture Overview
• The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer
• The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
• The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
• Timing Analyzer: Introduction to Timing Analysis
• Timing Closure with Intel® Quartus® Prime Pro Software
• Using Fast Forward Compile for the Intel® HyperFlex™ Architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Advanced Optimization with Intel® Hyperflex™ Architecture
• Hyper-Optimization Techniques 2: Pre-Computation
• Hyper-Optimization Techniques 3: Shannon’s Decomposition
• Intel® Stratix® 10 FPGA Optimization: Loop Analysis and Solutions
• Introduction to Hyper-Optimization

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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