Serial RapidIO Design with Altera 40nm Devices (Legacy Course) (ORIO1115)

79 Minutes Online Course

Course Description

This online course will instruct you in how to build Serial RapidIO™ solutions targeting Altera® 40-nm devices with embedded transceivers using the Quartus® II software. In this course, you will learn how to configure the Altera RapidIO MegaCore® IP function for your RapidIO-based design and connect it to the system interconnect fabric using the SOPC Builder tool. You will also learn how to directly configure the transceivers for a physical-layer only implementation, so you can connect your own custom RapidIO logical and transport layer blocks. If you choose, you may download detailed exercise instructions, so that you can practice developing and verifying a custom protocol solution using the Quartus® II software and ModelSim®-Altera® simulation tool.

At Course Completion

You will be able to:

  • Describe the features and functionality of the RapidIO MegaCore IP function when using 40-nm devices with transceivers
  • Configure a Serial RapidIO design block and incorporate into an SOPC Builder system
  • Describe how the RapidIO core interfaces with the system interconnect fabric
  • Configure the embedded transceiver for a custom RapidIO solution

Skills Required

  • Understanding of the RapidIO technology specifications
  • Familiarity with common high-speed transceiver architecture OR viewing the following course: Transceiver Basics
  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus II design software
  • Some familiarity with SOPC Builder (if using the SOPC Builder flow)

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

Class Schedule

Result Showing 1

On-lineAnytimeFreeRegister Now