Course DescriptionThis training is part 2 of 2. The Platform Designer system integration tool, formerly known as Qsys, saves design time and improves productivity by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. In this training, you'll finish the system by making connections between component interfaces, setting up base addresses for memory-mapped slaves, and reviewing the system design. You'll then generate the system HDL files and incorporate the design in the Intel® Quartus® Prime software FPGA design flow. This training includes a lab exercise with instructions and files that are designed for the Intel® Quartus® Prime software, version 17.1, and the Terasic Cyclone® V GX starter kit.
At Course Completion
You will be able to:
- Create a system design in the Platform Designer user interface
- Incorporate your Platform Designer system into an Intel® Quartus® Prime project for compilation
- Familiarity with FPGA/CPLD design flow
- Working knowledge of the Intel® Quartus® Prime software