Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: Optimization (OPWRA10S103)

51 Minutes Online Course

Course Description

This is part 3 of 4. Designing for low-power in today’s high-speed Intel Stratix 10 and Arria 10 FPGA designs is more important than ever. Knowing the final design’s power usage early in the design process is necessary for making power supply and device cooling decisions. This training will give you the knowledge and tools you need to perform highly accurate estimates of power usage and what to do to optimize power. In this third part, you'll learn many different techniques for optimizing a design for power, from simple settings adjustments to perform a power-driven compilation in the Intel Quartus Prime software, to making design changes that affect how the design gets compiled.

At Course Completion

You will be able to:

  • Analyze and optimize power usage in all stages of the FPGA design process for Intel Arria 10 and Intel Stratix 10 devices
  • Understand the differences between static and dynamic power and how they are analyzed by the tools
  • Optimize power by performing a power-driven compilation and by following low-power design guidelines

Skills Required

  • Completion of “Using the Quartus Prime Software: An Introduction” OR a basic understanding of the FPGA design flow and the Intel Quartus Prime software
  • Basic understanding of timing analysis
  • Basic knowledge of performing simulations in 3rd-party EDA simulation tools

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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