Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: Intro & Early Power Estimator (OPWRA10S101)

55 Minutes Online Course

Course Description

This is part 1 of 4. Designing for low-power in today’s high-speed Intel Stratix 10 and Arria 10 FPGA designs is more important than ever. Knowing the final design’s power usage early in the design process is necessary for making power supply and device cooling decisions. This training will give you the knowledge and tools you need to perform highly accurate estimates of power usage and what to do to optimize power. In this first part, you’ll learn the basics of power analysis, including a detailed look at analyzing static and dynamic power. You'll also learn how to perform an early power estimate with the EPE spreadsheet and how this powerful tool can be used at any stage of the FPGA design process.

At Course Completion

You will be able to:

  • Analyze and optimize power usage in all stages of the FPGA design process for Intel Arria 10 and Intel Stratix 10 devices
  • Understand the differences between static and dynamic power and how they are analyzed by the tools
  • Learn how the Early Power Estimator (EPE) spreadsheets allow for quick power analysis at any stage of development

Skills Required

  • Completion of “Using the Quartus Prime Software: An Introduction” OR a basic understanding of the FPGA design flow and the Intel Quartus Prime software
  • Basic understanding of timing analysis
  • Basic knowledge of performing simulations in 3rd-party EDA simulation tools


We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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