Introduction to the Intel® FPGA P-Tile (OPTILE)

29 Minutes Online Course

Course Description

Intel® Agilex™ F-Series and Intel Stratix® 10 DX FPGAs are packaged with Intel’s P-Tile transceiver tile, which implements the PCI Express* Gen3 and Gen4 standards. This training is the first step in learning how to build a high-speed interface using the P-Tile. You will begin by learning about Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology that makes packaging the P-Tile with the FPGA possible. You will then be introduced to the architecture and key features of the P-Tile including endpoint, root port, and transaction layer protocol (TLP) bypass modes, port bifurcation, autonomous hard IP (HIP) mode, and Single Root IO Virtualization (SR-IOV). The functional components of the tile will be described including the PMA, PCS, and configuration registers.

At Course Completion

You will be able to:

  • Describe the functional blocks found in the P-Tile including the PCS and PMA blocks
  • Understand the clocking configuration of the P-Tile
  • Describe the key features of the P-Tile including TLP bypass mode, port bifurcation, and SR-IOV

Skills Required

  • General understanding of transceivers
  • General understanding of PCI Express* protocol

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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