Partial Reconfiguration for 28nm Devices (OPR100)

69 Minutes Online Course

Course Description

In this class, you will learn about the Partial Reconfiguration (PR) capabilities of Intel® FPGAs. Starting in Intel 28nm devices, you are able to change the functionality of a portion of an active FPGA, while the rest of the FPGA operates uninterruptedly. During this training, you will explore the benefits of PR, understand the design guidelines involving PR, and know the steps necessary to enable this feature in the Quartus II software version 12.1.

At Course Completion

You will be able to:

  • Understand the Partial Reconfiguration design flow
  • Prepare a design for Partial Reconfiguration
  • Design a Partial Reconfiguration host
  • Create partial configuration files

Skills Required

  • Completion of "The Quartus II Software Design Series: Foundation" course OR a working knowledge of the Quartus II software
  • Knowledge of a Hardware Description Language
  • Completion of "Introduction to Incremental Compilation" course OR a working knowledge of incremental compilation
  • Completion of “Configuring Altera FPGAs” course OR a working knowledge of FPGA configuration schemes

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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