Introduction to the 28-nm Hard IP for PCI Express (OPCIINTRO)

37 Minutes Online Course

Course Description

Are you new to using the Hard IP for PCI Express® found in Cyclone® V, Arria® V and Stratix® V devices? If so, then you should start with this course. In this class, you will learn the capabilities and features of the Hard IP for PCI Express to see why it is the right solution for your PCI Express design. You will learn the core variations that are available to help you decide which variation is the best based on your design requirements.

At Course Completion

You will be able to:

  • Describe the basic and advanced features of the Hard IP for PCI Express block found in select Altera® 28nm devices
  • Select between the different Hard IP for PCI Express core variations based on performance and required features

Skills Required

  • Some understanding of the PCI Express Protocol specification is helpful, but not required
  • Familiarity with common high-speed transceiver architecture OR viewing the following Transceiver Basics course OR attending the Building Gigabit Interfaces in Altera Transceiver Devices
  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus II design software

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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