Designing with Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX Hard IP for PCI Express* (OPCIDESIGNG10)

31 Minutes Online Course

Course Description

In this class, you will learn rules that must be followed to ensure proper placement of Intel® Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 GX FPGA Hard IP for PCI Express* blocks and transceiver channels, failure of which can lead to compilation errors and possibly board re-spins. You will learn how to select the best clock resource based on location along with PCI Express lane speed and configuration. You will learn how to set up and use Configuration via Protocol (CvP) using PCI Express to configure your target FPGA over the PCI Express link. You will also learn debugging tools and techniques to employ if issues arise when bringing up your PCIe link in a system.

At Course Completion

You will be able to:

  • Avoid board-level issues when choosing locations for Hard IP for PCI Express transceiver channels
  • Selecting the right PLL for low-jitter transmit operation
  • Enable CvP in your Intel Stratix 10, Intel Arria 10 and Intel Cyclone 10 GX FPGA
  • Describe the tools and techniques used to debug a Hard IP design

Skills Required

  • Some understanding of the PCI Express* Protocol specification is useful, but not required
  • Familiarity with common high-speed transceiver architecture OR viewing the following Transceiver Basics course OR attending the Building Gigabit Interfaces in Intel Arria 10 Transceiver Devices
  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Intel Quartus Prime Pro design software

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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