Customizing Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX FPGA Hard IP for PCI Express* (OPCICUSTOMG10)
Course Description
In this course, you will learn how to customize the Hard IP PCI Express* when building a PCI Express Endpoint or Root Port design targeting the Intel Stratix 10, Intel Arria 10 or Intel Cyclone 10 GX FPGA devices. You will see how to select options in the Hard IP parameter editor to customize the Hard IP per your specific design requirements. To use the parameter editor, you will learn about two flows in which to incorporate the Hard IP into an FPGA design, using the IP Catalog found in the Platform Designer system building tool or the IP Catalog found in the Intel Quartus® Prime Pro development suite.
At Course Completion
You will be able to:
- Create a PCI Express design in an Intel Stratix 10, Intel Arria 10 or Intel Cyclone 10 GX FPGA using
- 1) Platform Designer system design tool
- 2) Intel Quartus Prime Pro IP Catalog
- Customize your Intel FPGA Hard IP for PCI Express instance using IP parameter editor
Skills Required
- Some understanding of the PCI Express Protocol specification is helpful, but not required
- Familiarity with common high-speed transceiver architecture OR viewing the Transceiver Basics course
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus Prime Pro software
Prerequisites
We recommend completing the following courses:
- Building Interfaces with Arria 10 High-Speed Transceivers
- Intel® Stratix® 10 FPGA L- and H-Tile Transceiver Basics
- Introduction to the Arria 10 Hard IP for PCI Express
- The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
- The Intel® Quartus® Prime Software: Foundation (Pro Edition) (Online Training)
- Transceiver Basics for 20 nm and 28 nm Devices
- Using the Intel® Quartus® Prime Standard Edition Software: An Introduction
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: