Customizing the 28-nm Hard IP for PCI Express (OPCICUSTOM)

35 Minutes Online Course

Course Description

p>In this class, you will learn how to use the Qsys system design tool to build a PCI Express® Endpoint or Root Port design containing the Cyclone® V, Arria® V or Stratix® Hard IP for PCI Express. You will see how to select options in the Hard IP parameter editor to customize the Hard IP per your specific design requirements. As an alternative, you will discover how the Quartus® II IP Catalog can be used as another method for building your PCI Express design.

At Course Completion

You will be able to:

  • Use Qsys system design tool to create a PCI Express design in an Altera 28 nm FPGA using the Hard IP for PCI Express
  • Customize your Hard IP instance using IP parameter editor
  • Create a PCI Express design using the Quartus II IP Catalog flow

Skills Required

  • Some understanding of the PCI Express Protocol specification is helpful, but not required
  • Familiarity with common high-speed transceiver architecture OR viewing the following Transceiver Basics course OR attending the Building Gigabit Interfaces in Altera Transceiver Devices
  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus II design software
  • Some familiarity with the Qsys design tool is helpful, but not required

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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