OpenCL™ Coding Optimizations for Intel® Stratix® 10 Devices (OOPNCLS10)
Course Description
In this course, we will cover how the offline kernel compiler of the Intel® FPGA SDK for OpenCL™ optimizes OpenCL kernel code for optimal performance on Intel® Stratix® 10 FPGAs and how to use recommended coding constructs to enable these optimizations. Most of this class covers the differences in behavior of the kernel compiler when targeting Intel Stratix 10 devices with Hyperflex™ architecture when compared to earlier device families. Vast majority of the OpenCL kernel coding optimizations that apply to earlier device families are still applicable to Intel Stratix 10 devices and are not covered in this training.At Course Completion
You will be able to:
- Understand how the offline kernel compiler in the Intel FPGA SDK for OpenCL optimizes constructs for the Intel Stratix 10 Hyperflex architecture
- Employ coding recommendations for best performance on Intel Stratix 10 devices. Recommendations include 1) channels and pipes usage, 2) enable loop orchestration optimization, 3) pre-computation to reduce loop dependency feedback, 4) local memory recommendations, 5) avoid constructs that prevent new datapath control pipelining, and 6) RTL library
Skills Required
- Understanding of basic optimization techniques for the Intel FPGA SDK for OpenCL
- Completion of “Memory Optimization for OpenCL on Intel FPGAs” online training
- Completion of “Using Channels and Pipes with OpenCL on Intel FPGAs” online training
- Completion of “OpenCL: Single-Threaded vs Multi-Threaded Kernels” online training
Prerequisites
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
Class Schedule
Result Showing 1
| Location | Dates | Price | Registration |
|---|---|---|---|
| On-line | Anytime | Free | Register Now |