Memory Optimization for OpenCL™ on Intel® FPGAs (OOPNCLMEMOPT)

48 Minutes Online Course

Course Description

This course covers memory optimization techniques for OpenCL™ solution on FPGAs. Learn an overview of global, constant, local & private caching. Using the HTML report to look at the system architecture, kernel memory structure, & system area will be covered. For each type of memory, optimization strategies for performance & area will be explained & code examples demonstrate how to use them. Techniques include banking, coalescing, merging, & replication. Writing code that the Intel® FPGA SDK for OpenCL kernel compiler (aoc) can automatically optimize will be stressed. Manual addition of attributes & pragmas to your code will be discussed. This includes a lab exercise which will give you hands-on practice. *OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of Khronos

At Course Completion

You will be able to:

  • List and define the types of memory defined by the OpenCL specification
  • Write OpenCL kernel code that the compiler can efficiently analyze
  • Improve performance of memory architectures through attributes
  • Improve host-device communication efficiency

Skills Required

  • A basic knowledge of OpenCL kernel code and host code
  • A basic knowledge of how to run the Intel FPGA SDK for OpenCL

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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