This online training discusses two different ways of creating effective pipelining solutions with OpenCL™ on FPGA accelerators. We will talk about how NDRange or multi-threaded kernels, where programmers explicitly implement the kernel in a data-parallel way, are mapped on to the FPGA as well as how single-threaded kernels, where the compiler extracts parallelism automatically with loop pipelining, are executed on the FPGA. We will discuss the various advantages and disadvantages of each method and walkthrough a FIR design example to illustrate the difference.
*OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of Khronos.
At Course Completion
You will be able to:
- Describe how NDRange kernels are mapped to FPGAs
- Understand the concept of loop-pipelining in single-threaded kernels and how loop carried dependencies are handled
- Understand the advantages and limitations of both types of kernels
- Know when to use single-threaded tasks vs multi-threaded NDRange kernels
- Basic OpenCL coding knowledge
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
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