On-Chip Debugging of Memory Interfaces IP in Intel® FPGA Devices (OMEM1124)

Course Description

This training is part 4 of 4. Intel® Stratix® 10, Arria® 10, and Cyclone® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps on some devices. This part of the training discusses the use of the EMIF Debug Toolkit and the On-Chip Debug Port. As on previous device families, these tools provide runtime information through a JTAG connection or through software control on the calibration and available margin in a memory interface. Due to the changes in the memory architecture from previous devices, this training also discusses the system design changes required to use these tools with designs that include multiple memory interfaces.

At Course Completion

You will be able to:

• Perform on-chip debugging of a memory interface using the EMIF Toolkit or the On-Chip Debug Toolkit
• Configure a design with multiple memory interfaces to work with these tools

Skills Required

• Background in digital logic design
• Basic knowledge of memory interfaces
• Familiarity with the Intel® Quartus® Prime software
• Familiarity with memory interfaces in Intel FPGA devices from the listed prerequisite training classes

Prerequisites

We recommend completing the following courses:

• Integrating Memory Interfaces IP in Intel® FPGA Devices
• Introduction to Memory Interfaces IP in Intel® FPGA Devices
• Using High Performance Memory Interfaces in Altera 28-nm and 40-nm FPGAs
• Verifying Memory Interfaces IP in Intel® FPGA Devices

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Signal Tap Logic Analyzer: Introduction & Getting Started
• Timing Analyzer: Introduction to Timing Analysis

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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