Verifying Memory Interfaces IP in Intel® FPGA Devices (OMEM1123)
Course Description
This training is part 3 of 4. Intel® Stratix® 10, Arria® 10, and Cyclone® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps on some devices. This part of the training discusses how to perform a simulation of the altera_emif IP either by itself or using the generated example design. When generated, the IP creates all the files needed to perform a simulation. Timing analysis of the IP is also discussed along with suggestions for timing closure. The hard resources used for altera_emif along with easier-to-read timing reports simplifies analysis and closure.At Course Completion
You will be able to:
- Verify the functionality of an Intel® FPGA EMIF design through simulation
- Perform a normal timing analysis or use the new early I/O timing analysis
Skills Required
- Background in digital logic design
- Basic knowledge of memory interfaces
- Familiarity with the Intel® Quartus® Prime software
- Familiarity with memory interfaces in Intel FPGA devices from the listed prerequisite training classes
Prerequisites
We recommend completing the following courses:
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: