Introduction to Memory Interfaces IP in Intel® FPGA Devices (OMEM1121)

Course Description

This training is part 1 of 4. Intel® Stratix® 10, Arria® 10, and Cyclone® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps on some devices. This first part of the training introduces the memory options available and describes how the architecture makes such performance possible. It also describes the unique features of the built-in hard memory controller needed to achieve such speeds.

At Course Completion

You will be able to:

• Know the external memory interface (EMIF) options available in the latest Intel® FPGA devices
• Understand the new architectural features for implementing memory interfaces
• Learn about the features of the new hard memory controller that make higher speed interfaces possible

Skills Required

• Background in digital logic design
• Basic knowledge of memory interfaces
• Familiarity with the Intel® Quartus® software
• Familiarity with memory interfaces in Intel FPGA devices from either of the listed prerequisite training classes

Prerequisites

We recommend completing the following courses:

• Implementing, Simulating, and Debugging External Memory Interfaces (Legacy Course)
• Using High Performance Memory Interfaces in Altera 28-nm and 40-nm FPGAs

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Integrating Memory Interfaces IP in Intel® FPGA Devices
• On-Chip Debugging of Memory Interfaces IP in Intel® FPGA Devices
• Signal Tap Logic Analyzer: Introduction & Getting Started
• Timing Analyzer: Introduction to Timing Analysis
• Verifying Memory Interfaces IP in Intel® FPGA Devices

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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