Using High Performance Memory Interfaces in Altera 28-nm and 40-nm FPGAs (OMEM1110)

117 Minutes Online Course

Course Description

Memory interface design for FPGAs has traditionally been a complex process. This training will highlight the ease with which high performance memory interfaces can be implemented and tested in Altera 28-nm and 40-nm devices (Stratix® IV, Stratix V, Cyclone® IV, Cyclone V, Arria® II GX, and Arria V devices) using the Quartus® II software v. 12.1. You’ll learn how to select, parameterize, and test your memory controller IP easily by following a recommended design flow. This training focuses on creating DDR-style memory interfaces using Altera’s UniPHY self-calibrating PHY block. This PHY can be used with Altera’s memory controller IP or combined with your own custom controller.

At Course Completion

You will be able to:

  • Parameterize high-performance Altera® memory controller IP
  • Understand the advantages of using the UniPHY auto-calibrated PHY in a design
  • Instantiate and test high-performance memory controller IP in your design
  • Set up and run an RTL simulation in the ModelSim®-Altera Starter Edition software
  • Perform a static timing analysis with the TimeQuest timing analyzer
  • Correct some common timing problems
  • Use on-chip debugging tools to debug interface calibration and functionality

Skills Required

  • Background in digital logic design
  • Basic knowledge of memory interfaces
  • Familiarity with the Quartus II software
  • Familiarity with a simulation tool, such as the ModelSim-Altera Starter Edition
  • Prior exposure to the TimeQuest timing analysis tool

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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