JESD204B MegaCore IP Overview (OJESDOVERVIEW)

Course Description

This online course will provide a broad overview of the JESD204B MegaCore® IP. In order to make sure that you understand all the terms and concepts used in the course, we begin with a discussion of the relevant portions of the JESD204B interface specification. Next, some of the important features of the JESD204B MegaCore IP are presented. Finally, data flow through the system is used to describe the functional details of the core.

At Course Completion

You will be able to:

• Describe the features and functionality of the JESD204B MegaCore IP

Skills Required

• Understanding of the JESD204B specification
• Familiarity with common high-speed transceiver architecture OR viewing the following course: "Transceiver Basics"
• Familiarity with FPGA/CPLD design flow
• Familiarity with the Quartus® Prime design software
• Some familiarity with Qsys

Prerequisites

We recommend completing the following courses:

• Transceiver Basics for 20 nm and 28 nm Devices

Related Courses

Below are the related courses you may be interested in:

• Building Gigabit Interfaces in 28-nm Devices
• Building Interfaces with Arria 10 High-Speed Transceivers

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• I/O Interfaces

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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