Creating Reusable Design Blocks: IP Integration with the Intel® Quartus® Prime Software (OIPR1002)

16 Minutes Online Course

Course Description

This training is part 3 of 3. As FPGA designs get larger and more complicated, intellectual property (IP) is being used more often to help reduce time-to-market. Including IP allows designers to focus on new aspects of their design and improve existing designs instead of spending time recreating what’s been done before. But what if you want to create your own IP? This training discusses how best to create your IP so it will easily integrate into a design in the Intel® Quartus® Prime software. It also presents final aspects of the IP design process, such as documentation and creating a GUI interface using the Platform Designer Component Editor. The training also includes an IP development checklist to help manage everything needed for distributing your IP.

At Course Completion

You will be able to:

  • Follow design recommendations for easy integration into the Intel® Quartus® Prime software
  • Provide useful documentation for your IP
  • Create a GUI interface for your IP using the Platform Designer Component Editor

Skills Required

  • Background in digital logic design
  • Familiarity with an HDL language (Verilog or VHDL)
  • Familiarity with the Intel® Quartus® Prime software
  • Familiarity with Tcl scripting
  • Some familiarity with SDC timing constraints

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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