Creating Reusable Design Blocks: IP Design & Implementation with the Intel® Quartus® Prime Software (OIPR1001)

29 Minutes Online Course

Course Description

This training is part 2 of 3. As FPGA designs get larger and more complicated, intellectual property (IP) is being used more often to help reduce time-to-market. Including IP allows designers to focus on new aspects of their design and improve existing designs instead of spending time recreating what’s been done before. But what if you want to create your own IP? This training focuses on all aspects of how to create good reusable IP, including the IP user flow, the creation of IP files, the packaging of the IP, as well as other important factors to consider during the creation process.

At Course Completion

You will be able to:

  • Create IP that works within the typical IP user flow
  • Follow recommended packaging techniques, including file and signal naming conventions
  • Manage the creation and use of parameters for IP customization

Skills Required

  • Background in digital logic design
  • Familiarity with an HDL language (Verilog or VHDL)
  • Familiarity with the Intel® Quartus® Prime software
  • Familiarity with Tcl scripting
  • Some familiarity with SDC timing constraints

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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