Course DescriptionIn this training, you will learn about the incremental optimization and per-stage compilation features of the Intel® Quartus® Prime Pro edition software. The per-stage compiler is designed to help customers achieve maximum productivity by helping to reduce design iterations and compile time during the process of optimizing an FPGA design. In this training, you will learn about the benefits of using these features and how to use them in the Intel Quartus Prime Pro Edition software.
At Course Completion
You will be able to:
- Understand the advantages of a modular compilation process
- Execute the individual compilation steps of the per-stage compiler
- Perform incremental optimizations after various compilation stages
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus Prime design software