Incremental Block-Based Compilation in the Intel Quartus® Prime Pro Software: Design Partitioning (OIBBC101)
Course Description
This training is part 2 of 3. Designing, organizing, and optimizing a large FPGA design can be difficult and time consuming. Every change made to fix a problem or to help close timing requires the design to be completely recompiled. Not only can this take a long time, but the placement and routing of untouched parts of the design can be affected. In this training, you will learn about incremental block-based compilation, the ability to partition your design and choose which parts should be reused in subsequent compilations. This feature will help you reduce compile times, preserve performance, and close timing faster. This part of the training goes into detail on how to plan for design partitioning, guidelines for creating good partitions, and the Intel Quartus Prime tools used.At Course Completion
You will be able to:
- Set up and perform incremental block-based compilation through design partition creation in the Quartus® Prime Pro Edition software
- Understand the different design flows (top-down, bottom-up) for implementing a block-based design
- Preserve compiled design partitions by reusing previous compilation results in a single project
Skills Required
- Basic knowledge of the Quartus Prime software
- Knowledge of creating FPGA designs in a hardware description language (Verilog or VHDL)
Prerequisites
We recommend completing the following courses:
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Related Courses
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: