HLS Coding Optimizations for Intel® Stratix® 10 Devices (OHLSS10)

17 Minutes Online Course

Course Description

In this course, we will cover how the Intel® High-Level Synthesis Compiler optimizes C++ code for optimal performance on Intel® Stratix® 10 FPGAs and how to use recommended coding constructs to enable these optimizations. Most of this class covers the differences in behavior of the Intel® HLS Compiler when targeting Intel Stratix 10 Device with Hyperflex™ architecture when compared to earlier device families. Vast majority of the HLS coding optimizations that apply to earlier device families are still applicable to Intel Stratix 10 devices and are not covered in this training.

At Course Completion

You will be able to:

  • Understand how the Intel HLS Compiler optimizes constructs for the Intel® Stratix® 10 Hyperflex™ architecture
  • Employ coding recommendations for best performance on Intel Stratix 10 devices. Recommendations include 1) stream usage, 2) enable loop orchestration optimization, 3) pre-computation to reduce loop dependency feedback, 4) avoid double-pumped memories, 5) and avoid constructs that prevent new datapath control pipelining.

Skills Required

  • Familiarity with the Intel® HLS Compiler Optimization Techniques
  • Completion of the “High-Level Synthesis Advanced Optimization Techniques” course or equivalent online trainings

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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