HLS Performance Optimization (Part 6 of 7) (OHLS6)

Course Description

In the class, you will learn how to use common methodology and techniques to boost the performance of your HLS component. We will walk through the optimization process, covering interface selection, loop optimizations, memory optimizations, and data type selection. Download a PDF of the presentation here: http://www.altera.com/customertraining/Videos/HLSPart6.zip

At Course Completion

You will be able to:

• Create a high-performance HLS component using common optimization techniques
• Examine the impact of those optimizations on performance as measured in latency as reported through the cosimulation flow

Skills Required

• Basic understanding of the C++ programming language
• Basic understanding of FPGAs and the Intel Quartus Development Environment

Prerequisites

We recommend completing the following courses:

• HLS Data Types (Part 4 of 7)
• HLS Interfaces (Part 2 of 7)
• HLS Local Memory Optimizations (Part 5 of 7)
• HLS Loop Optimizations (Part 3 of 7)
• Introduction to High-Level Synthesis (Part 1 of 7)

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• HLS Optimization Example: Matrix Decomposition (Part 7 of 7)

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• SW Developer for C Programming - 200 Level

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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