HLS Local Memory Optimizations (Part 5 of 7) (OHLS5)

Course Description

In the class, you will learn how to effectively optimize local memory inside an HLS component. We will cover how the compiler tries to automatically create stall-free memory architectures for local memory. We will discuss how to use attributes to specify memory structure, and we’ll talk about how some array structures are converted to registers. Download a PDF of the presentation and a hands-on lab exercise here: http://www.altera.com/customertraining/Videos/HLSPart5.zip

At Course Completion

You will be able to:

• Understand how the HLS compiler create local memory architectures
• Use attributes to create the optimal local memory
• Use effective techniques to implement arrays in registers

Skills Required

• Basic understanding of the C++ programming language
• Basic understanding of FPGAs and the Intel Quartus Development Environment

Prerequisites

We recommend completing the following courses:

• HLS Data Types (Part 4 of 7)
• HLS Interfaces (Part 2 of 7)
• HLS Loop Optimizations (Part 3 of 7)
• Introduction to High-Level Synthesis (Part 1 of 7)

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• HLS Performance Optimization (Part 6 of 7)

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• SW Developer for C Programming - 200 Level

Class Schedule

Result Showing 1

Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

Request a class in your region.