HLS Loop Optimizations (Part 3 of 7) (OHLS3)

82 Minutes Online Course

Course Description

In the class, you will learn how to use the Intel® HLS Compiler to optimize loops in your HLS component. We will cover the basic concepts of loop pipelining and loop unrolling and present common techniques to optimize your loops. Download a PDF of the presentation and a hands-on lab exercise here: http://www.altera.com/customertraining/Videos/HLSPart3.zip

At Course Completion

You will be able to:

  • Understand loop execution model
  • Use common techniques to improve the pipeline performance of loops
  • Effectively use pragmas to improve the performance of loops
  • Resource share using loops

Skills Required

  • Basic understanding of the C++ programming language
  • Basic understanding of FPGAs and the Intel Quartus Development Environment


We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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