Introduction to High-Level Synthesis (Part 1 of 7) (OHLS1)

Course Description

In the class, you will learn how to use the Intel® HLS Compiler to synthesize and verify IP components for Intel FPGAs. We will first discuss the benefits of HLS then talk about features of the Intel HLS Compiler. You will learn how to use the Intel HLS compiler to perform emulation functional debug, co-simulation with a behavioral simulator and finally integrate the generated IP within an Intel Quartus® software project. Download a PDF of the presentation and a hands-on lab exercise here: https://www.intel.com/content/www/us/en/programmable/customertraining/Videos/HLSPart1.zip

At Course Completion

You will be able to:

• Use the Intel HLS Compiler to synthesize a component compatible with the Intel Quartus Prime software design flow
• Co-simulate your HLS component using an RTL simulator with a software testbench
• Integrate the HLS component within an FPGA design

Skills Required

• Basic understanding of the C++ programming language
• Basic understanding of FPGAs and the Intel Quartus Prime Software

Prerequisites

We recommend completing the following courses:

• Basics of Programmable Logic: FPGA Architecture
• Using the Intel® Quartus® Prime Standard Edition Software: An Introduction

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• HLS Interfaces (Part 2 of 7)

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• SW Developer for Acceleration using C/C++ - 200 Level

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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