Creating High-Performance Designs in 20 nm Intel® FPGAs (OHIPERF20NM)

41 Minutes Online Course

Course Description

Intel® Arria® 10 and Cyclone® 10 GX FPGAs internal clocks can run at speeds over 600 MHz. To reach these clock speeds, FPGA designers must employ good design practices that enable high-performance. These design practices include RTL coding style, device resource management and layout control. This course discusses these topics and provides recommendations to use in maximizing FPGA performance.

At Course Completion

You will be able to:

  • Making RTL coding decisions for high performance clocks
  • Manage use of 20 nm logic, routing, memory, multiplier and clocking resources
  • Create a floorplan for a high-performance 20 nm design

Skills Required

  • Familiarity with Arria® 10 and Cyclone® 10 GX FPGA architecture
  • Familiarity with the Quartus® Prime Pro software design flow and features

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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