Creating High-Performance Designs in Intel® Stratix® 10 FPGAs (OHIPERF14NM)

45 Minutes Online Course

Course Description

Intel® Stratix® 10 FPGA internal clocks can run at speeds over 600 MHz. To reach these clock speeds, FPGA designers must employ good design practices that enable high-performance. These design practices include RTL coding style, device resource management and layout control. This course discusses these topics and provides recommendations to use in maximizing FPGA performance.

At Course Completion

You will be able to:

  • Making RTL coding decisions for high performance clocks
  • Manage use of Intel Stratix 10 FPGA logic, routing, memory, multiplier and clocking resources
  • Create a floorplan for a high-performance Intel Stratix 10 FPGA design

Skills Required

  • Familiarity with Intel Stratix 10 FPGA architecture
  • Familiarity with the Intel Quartus® Prime Pro software design flow and features

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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