Best Design Practices for Timing Closure (OHDL1130)

50 Minutes Online Course

Course Description

Learn how to address timing closure issues with HDL design techniques. This training will discuss the problem of timing closure and why it is important to plan for it. You will learn about common timing closure issues. You will see how to fix example timing closure situations by changing how the functionality is coded. You will learn how the Intel® Quartus® Prime Design Software can assist you with this goal.

At Course Completion

You will be able to:

  • Identify HDL constructs that can cause problems in timing closure
  • Address such issues by suitable changes in the HDL code

Skills Required

  • Background in digital logic design
  • An understanding of basic FPGA design flow
  • Basic understanding of the Intel Quartus Prime user interface
  • Basic understanding of Verilog HDL or VHDL coding

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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