Verilog HDL Basics (OHDL1120)

50 Minutes Online Course

Course Description

This course will provide an overview of the Verilog hardware description language (HDL) and its use in programmable logic design. The emphasis is on the synthesis constructs of Verilog HDL; however, you will also learn about some simulation constructs. You will gain a basic understanding of Verilog HDL that will enable you to begin creating your design. The ModelSim* for Intel® FPGA Edition Software v. 10.1d is used for demonstration purposes.

At Course Completion

You will be able to:

  • Understand the origin of the Verilog HDL language
  • Understand the language basics
  • Use Verilog HDL building blocks (design units) including modules, ports, processes, and assignments
  • Model code styles including behavioral code style and structural code style
  • Understand the design methodologies of Verilog HDL and the differences between simulation models and synthesis models

Skills Required

  • Background in digital logic design
  • Prior knowledge of a programming language (e.g., "C" language) is a plus
  • No prior knowledge of Verilog HDL or Intel® Quartus® Prime software is required