Course DescriptionThis online course will provide you with an overview of the VHDL language and its use in logic design. By the end of the course, you will understand the basic parts of a VHDL model and how each is used. You will also gain an understanding of the basic VHDL constructs used in both the synthesis and simulation environments. You will also be able to build complete logic structures that can be synthesized into programmable logic device hardware. Lastly, you gain the understanding required to connect entire models together to create hierarchical designs.