Generation 10 Transceiver Clocking (OG10XCVRCLK)

28 Minutes Online Course

Course Description

In the Generation 10 Transceiver Clocking course, you will learn the architecture of the clocking resources found in Altera® Arria® 10 high-speed transceivers. By learning this architecture, you will be able to maximize your transceiver channel usage, possibly leading to a cost reduction by using a smaller FPGA with lesser transceiver channels. You will also be able to avoid transceiver design issues by applying an understanding of transceiver clocking structure.

At Course Completion

You will be able to:

  • Describe the Arria® 10 transceiver clocking structure
  • Select a successful transceiver layout based on the clocking resources available
  • Avoid compilation errors by making valid clock connections

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with FPGA architecture
  • Knowledge of Arria® 10 transceiver architecture
  • Familiarity with high-speed interfaces and transmission protocols is helpful, but not required

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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