Reducing Compile Time with Fast Preservation (OFASTPRES)

46 Minutes Online Course

Course Description

Everybody wants to reduce their compile times. Whether debugging or optimizing a design to meet timing, you want to get back to testing and working with the design as quickly as possible. With the Fast Preservation feature enabled, you can exponentially reduce compile times in the Intel® Quartus® Prime Pro edition software when using a block-based design flow, such as design block reuse or partial reconfiguration (PR). This training shows you how to set up your project to make use of this feature whether you are already using a block-based design flow or not. Basic required concepts, such as design partitioning and floorplanning with Logic Lock regions are reviewed, but see the recommended prerequisites for more details.

At Course Completion

You will be able to:

  • Know the advantages of using the Fast Preservation feature in a block-based design flow
  • Set up a design to make use of the feature to greatly reduce compile times

Skills Required

  • Background in digital logic design
  • Familiarity with the Intel® Quartus® Prime software
  • Familiarity with the main block-based design flows: partial reconfiguration, design block reuse, or incremental block-based compilation

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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